Verific Comments on Open Source Release of Synopsys VMM Methodology

Verific Design Automation announced ongoing support for the VMM methodology, originally developed by Synopsys and released into the public domain today. As the primary supplier of SystemVerilog, Verilog and VHDL software front ends to electronic design automation (EDA), field programmable gate array (FPGA) and semiconductor vendors, Verific has offered VMM support in its SystemVerilog analyzer and elaborators since 2006. It was an early VMM Catalyst Member. Notes Rob Dekker, Verific's founde